Know the team before you walk in
You can't be impressive about work you can't place. This is the playbook: who this team actually is, what they ship, what the job is once you decode the JD, and how to make the manager round concrete.
Who the team is
The Cambridge office is the former Solarflare team, now part of AMD's Network Solutions Group. Solarflare built ultra-low-latency Ethernet NICs widely used in high-frequency trading and exchange infrastructure. The lineage is the whole story:
- Solarflare — low-latency Ethernet NICs, R&D in Cambridge. Famous in HFT, where shaving microseconds off send/receive is worth real money.
- Xilinx acquires Solarflare (2019) — brings in FPGA / silicon DNA. This is the “model the RTL” heritage in your JD.
- AMD acquires Xilinx (2022) — the Cambridge crew lands at AMD this way.
- AMD acquires Pensando (2022, $1.9B) — programmable DPUs for cloud / hyperscale. Together with Solarflare this forms the Network Solutions Group.
What they build
Network interface cards and the software that drives them — a smart NICthat plugs into a server's PCIe slot, handles networking, and offloads work the CPU would otherwise do.
X4 series NICs
Recent low-latency line: X4522 (dual SFP56, up to 50GbE) and X4542 (dual QSFP56, up to 100GbE), PCIe Gen5 x8, passively cooled under 25W.
CTPIO
Cut-Through Programmed IO — a packet starts transmitting before it has finished crossing the PCIe bus. That's the latency obsession this team lives in.
Onload
Their signature kernel-bypass stack — implements TCP/UDP in userspace so apps talk to the NIC directly, skipping the slow kernel path.
ef_vi
The layer-2 API under Onload: direct userspace datapath access to the NIC's RX/TX rings and event queue for very low latency. This is where ring buffers live.
The role, JD decoded
It's low-level C software at the boundary between the hardware and the operating system. Translate each JD phrase and you can speak to it:
| What the JD says | What it actually means |
|---|---|
| “software defined networking, network & storage offload, hardware datapath customization” | You write the software that controls how packets flow through the card and what work the card takes off the host CPU. |
| “working closely with the silicon team to refine the design and model the RTL” | You sit next to the chip designers and help model the next NIC's behaviour in software before the silicon physically exists (Xilinx/FPGA heritage). |
| “host driver teams to develop high performance network stacks” | You build and tune the fast path in the driver so it's as quick as possible (the Onload lineage). |
| “working with system test to take products to release” | You're involved end-to-end, from early design through to shipping. |
Mental model: a tight C / embedded team building the software for high-speed networking chips, shoulder-to-shoulder with the people designing the silicon, where latency and correctness at the hardware/software seam are everything. Not cloud-platform or web-scale SDN-controller work — close-to-the-metal systems software.
The interview process
Public reports (Glassdoor + a UK Cambridge write-up) describe the AMD senior-SWE loop fairly consistently:
- ~30-min HR / recruiter call — this is your Graham conversation.
- ~30-min hiring-manager call — a CV / resume overview. This is the round you make the pivot narrative land in.
- 4 × 45-min engineer interviews — one behavioural, the rest technical with live programming tasks (C, bit manipulation, pointers, embedded, atomics).
- Walk a packet end-to-end. Wire → NIC RX DMA → descriptor + event → poll → userspace → stack, and the reverse for send. See the datapath page.
- Bring two debugging stories. One data-corruption / race, one performance / tail-latency — each with the instrumentation you used and the root cause.
- Explain, don't just code. Reported across these teams: say the invariant and why behind a design (ring-buffer ownership, hardware constraints), then write it.
Where the team is going: AI networking
The biggest signal from adjacent Cambridge openings: it's now explicitly about AI systems, not just trading NICs. Graduate reqs on the same team describe networking for cloud and hyperscale data centre operators and AMD's AI systems. The Solarflare low-latency heritage is being pointed at AI cluster networking — connecting GPUs at scale, where the network is on the critical path for training and inference.
Names to drop (current, specific, impressive)
Pensando Pollara 400
AMD's first UEC-ready 400GbE AI NIC for back-end GPU-to-GPU scale-out. GA in 2025; Oracle the first cloud to deploy. Built on the Pensando P4 engine.
“Vulcano”
The next-gen NIC on the 2026 roadmap — 3nm, 800G, UALink host interface. Mentioning it shows you read the roadmap, not just the datasheet.
Ultra Ethernet (UEC)
Open Ethernet stack for AI/HPC scale-out: packet spray, out-of-order delivery with in-order completion, selective retransmission, path-aware congestion control.
UALink
The open scale-upaccelerator interconnect (1.0 spec, 2025; up to 1,024 accelerators). Pairs with UEC scale-out in AMD's “Helios” rack design.
How to be impressive in the manager round
The technical screen tests whether you can do the job. The manager round decides do I want this person on my team, will they stay, and can they think. Correctness is necessary but not what makes you memorable. Three high-leverage moves:
1. Lead with a clean pivot narrative
Your single highest-leverage move.
The manager's quiet worry: “PHY/wireless guy — will he actually thrive in Ethernet/TCP-IP driver work, or is he just escaping his current job?” Pre-empt it. Frame this as moving up the stack while staying at the metal, not switching fields:
That reframes you from “career-changer” to “same core engineer, adjacent domain.”
2. Tie yourself to where the team is going
AI cluster networking — see the section above.
Reference the AI-networking direction naturally. To name products without overclaiming, read three things before the call: the AMD Solarflare X4 product brief, the ef_vi section of UG1586, and the Pollara 400 product page. It shows you researched the team and that your growth goals line up with their strategy — what a manager most wants to hear from someone they'll invest in.
3. Bring a nasty-debug story from the HW/SW boundary
The JD stresses cross-team collaboration; show both.
Have one crisp story ready: a hard bug you chased across the hardware/software boundary — your methodology, the tools (gdb, perf, tracing, logic analyzer, RTL sim), and how you reasoned under hardware constraints. End it on how you collaborated across teams to land the fix. That single story hits “can they think” and “will they collaborate” at once.
The one gap to pre-empt
The JD wants Ethernet & TCP/IP and Linux device driversspecifically. If your protocol depth is more wireless-stack than TCP/IP, have a crisp story for how it transfers — and use this site's datapath and C question pages to close the gap before the call.
The number
The recruiter signalled he can get the offer to £70k base based on your interview. Two things to hold onto:
- £70k base is performance-gated.It's likely the top of the band for this req — a strong technical showing is literally what unlocks it versus landing lower. Every crisp answer on the ring buffer, the packet-parse, and the
volatile/memory-barrier distinction is justification to push to the top. - Base, not total. AMD pays base + annual bonus (~10–15% target) + RSUs. With £70k base, the package likely lands meaningfully higher. When numbers come up, ask plainly: “Is that base, and what do bonus and equity look like on top?”
- Level.The role is pitched “senior” but the bar is only ~2+ years (mid-level / SWE II). Your real PHY/embedded depth is substantive — make sure that lands so you're slotted at the top of the band, not the bottom.
- Visa.If sponsorship matters, confirm the current Skilled Worker salary rules and the role's SOC code with the recruiter — UK thresholds and exceptions change, so verify rather than assume.