The senior question bank
Past the fundamentals now. These are the tradeoff, failure-mode, and “why” questions that separate a senior from a mid-level engineer — one deep section per niche of this role, each with model answers, the trap being probed, and follow-ups.
Advanced C and Undefined Behavior
Probes whether a senior low-level engineer can reason about the C abstract machine, optimizer assumptions, ABI details, and real driver failure modes.
C11/C++11 Memory Model and Lock-Free Concurrency
Probes whether a senior engineer can connect language-level atomics to hardware ordering, progress guarantees, reclamation, and NIC datapath races.
CPU Microarchitecture for Low Latency
Probes whether the candidate can connect CPU ordering, caches, NUMA, and MMIO behavior to real NIC fast-path correctness and latency.
Performance and Latency Engineering
Probes whether the candidate can measure, explain, and reduce latency without fooling themselves or damaging correctness.
PCI Express for NIC Engineers
Probes whether a NIC engineer understands PCIe as a real transport with ordering, latency, interrupt, DMA, and platform failure modes rather than just a bus API.
DMA and IOMMU
Probes whether a low-level engineer can reason about DMA mappings, cache coherency, IOVA translation, barriers, and real Linux driver failure modes.
Linux Kernel Network Datapath
Probes whether a senior engineer can reason about Linux packet paths as a set of queues, cache lines, timers, memory ownership transitions, and observability tradeoffs.
Linux NIC Driver Craft
Probes whether a senior driver engineer can build and debug a NIC driver across PCI discovery, DMA ownership, NAPI, queues, locking, reset, and user-visible controls.
Kernel Bypass & Userspace Networking
Probes whether a senior engineer can reason from NIC rings, memory ordering, batching, flow steering, and real bypass APIs to production failure modes.
TCP/IP Stack Internals
Probes deep TCP/IP engineering judgment: state-machine edges, loss recovery, offloads, zero-copy, latency knobs, and packet-level debugging.
AI/HPC Cluster Networking
Probes whether a candidate can reason from verbs, PCIe, congestion, and collectives up to whole-cluster AI training behavior.
Datapath Data Structures & Allocators
Probes whether a candidate can design hot-path data structures that respect cache, memory ordering, concurrency, and packet-rate failure modes.
Confidentiality & Safe Disclosure
Practice for answering deep technical probes while protecting employer, customer, feature, metric, and internal-tooling confidentiality.
Debugging & Observability
A NIC-debugging round for a wireless-PHY embedded engineer pivoting into AMD networking: systematic packet-drop, latency, link, DMA, and datapath triage without overstating shipped Linux NIC-driver experience.