🧠 From NIC to DPU

8.1 The SmartNIC / DPU turn

The most striking thing about the 2019–2025 patents is the cast of characters. The same Cambridge architects who wrote the Onload and ef_vi canon — Steven Pope and David Riddoch — are still on the inventor lists, now joined by Jaideep Dastidar. But the object they describe has changed. It is no longer "a low-latency NIC that gets the kernel out of the way." It is a programmable data-plane computer: an FPGA-backed SmartNIC / DPU where packet processing, scheduling, security, and tenant isolation are all things the device does in hardware, at line rate, on behalf of a host that increasingly just hands work over and gets out of the way.

FPGA kernels inserted directly into the datapath. US12445395B2 (granted 2025, Pope/Riddoch/Roberts/Kitariev) describes a NIC with interface circuitry that links three things: host interface logic, NIC datapath logic, and host-offload circuitry — and the host-offload circuitry can hold FPGA applications or kernels placed directly into the receive and transmit paths. This is the logical endpoint of "split the datapath." In the Onload era, the split was host-software vs. NIC-hardware. Here, a per-frame programmable stage lives inside the RX/TX pipe itself, so processing can happen as the packet moves rather than after a round-trip through host software. The same questions ef_vi forced — who owns the queue, when does the host get told, how do you schedule device work against host work — reappear, just with a reprogrammable block now sitting in the middle of the pipe.

Tenants, zones, and heterogeneous blocks. Two Dastidar/Riddoch/Pope patents describe the DPU as a system, not a packet mover. US11995021B2 (zoned accelerator embedded processing) divides the device into isolated zones, with an I/O gateway that extracts bindings from packets and routes transactions to processing cores assigned to a given zone — multi-tenant isolation enforced inside one piece of silicon. US11983133B2 (adaptive integrated programmable DPU) is about composing heterogeneous blocks: fixed-function logic, processors, programmable logic, NoC-style on-chip communication, adaptors, and shared memory, all presented as a coherent device. Together they read as a thesis: a DPU is a small datacentre on a chip, and the hard part is keeping tenants apart while they share buffers, queues, and accelerators.

The datapath primitives, generalised. Underneath the new vocabulary, the old primitives are still load-bearing. US10983920B2 (customizable multi-queue DMA interface) lets user logic see and process descriptors from multiple queues directly — the same descriptor-ring and DMA machinery from the ef_vi chapter, now exposed to custom on-device logic. US11743134B2 (programmable traffic management engine) adds line-rate scheduling, shaping, policing, and flow classification with reusable fixed blocks plus programmable ones — the step from "move packets fast" to "enforce per-flow and per-tenant policy without burning host CPU." And US11983264B2 (adaptive acceleration of TLS, including key generation) makes encrypted transport a first-class datapath feature: if everything on the wire is TLS, a credible fast path cannot treat crypto setup and key-gen as someone else's problem.

Even the physical layout becomes a datapath decision. EP4298526A1 (spatial distribution in a 3D DPU, Dastidar) arranges packet buffers, sequencers, host/network interfaces, crypto, compression, processors, memory, and programmable logic across multiple physical layers, placed to minimise data movement and latency. It is the same instinct as the cache-locality patents from the kernel-bypass chapter, scaled up to 3D silicon floorplanning: where a buffer physically lives is a latency knob.

The throughline of the whole book holds. Queue ownership, DMA descriptors, memory registration, and backpressure are still the irreducible constraints — they did not go away when the NIC became a DPU. What got layered on top is isolation (zones, per-tenant routing) and orchestration (composing fixed and programmable blocks, scheduling traffic, managing keys). And this is precisely the seam where Miklos Reiter's background fits, honestly stated: he is not a named inventor on these datapath patents, but his Cambridge work on congestion pricing and resource allocation is exactly the modelling lens you need once a device has to share finite buffers, bandwidth, and accelerators fairly across competing tenants. The hardware enforces the policy; someone still has to decide what the policy should be.

Sources

• US12445395B2 — Network interface device
• US11995021B2 — Zoned accelerator embedded processing
• US11983133B2 — Adaptive integrated programmable data processing unit
• US10983920B2 — Customizable multi queue DMA interface
• US11743134B2 — Programmable traffic management engine
• US11983264B2 — Adaptive acceleration of transport layer security
• EP4298526A1 — Spatial distribution in a 3D data processing unit